An SDRAM is a conventional dynamic random access memory (DRAM) that has a synchronous interface. In the interface, external signals are latched by synchronizers at the rising edge of a clock signal, and are decoded to generate commands. Since it takes typically 2 to 3 nanoseconds for the latched signal to travel to the control circuits and to the x- or y-(column or row address) predecoders, the clock signal that triggers these control signals must be delayed with respect to the clock triggering the synchronizers. The delayed clock signal is generally referred to as DCLK and the undelayed clock signal is referred to as CLK.
DCLK is usually generated by a delay circuit, to which CLK is applied. The delay circuit is comprised of a delay chain and an output buffer, from which DCLK is received. When the number of SDRAM memory cells is not very large, and the operation frequency is not very high, this DCLK generator has worked well, and has the advantage of simplicity.
However, more recent SDRAMs are comprised of a much larger number of cells, for example 16 Mbits or larger, and work at high speed, for example 200 MHz or higher. The number of flip flops required in the control circuits for the SDRAM and in the address predecoders of the SDRAM becomes very large for SDRAMs having a large number of cells. This results in flip-flop gate capacitance and the routing wiring capacitance becoming large, which appears as a load on the clock signal. Since the AC power dissipation consumed by the clock signal is proportional to the capacitance in accordance with the formula P.sub.AC =C.sub.load V.sup.2 f.sub.c, where f.sub.c represents the clock frequency, C.sub.load represents the capacitance to be fed and V represents the voltage, it can be seen that the increased frequency of high speed SDRAMs as well as high cell count results in large AC power dissipation.
Thus it has been shown that a 200 MHz 16 Mbit SDRAM will consume more than 50 mA of current only for the DCLK buffer and the flip-flops clocked by DCLK, if the simple DCLK generator is used. This has made the simple DCLK generator scheme impractical to use.
Instead of the simple DCLK generator, a pulse generator can be used, followed by a latch instead of flip-flops. This reduces the number of flip-flops, but also results in the risk of the generation of glitches.
Another option is to lower the clock frequency, but this destroys the benefits of the high speed capability of such SDRAMs.